ASIC Design Engineer - Cache
Santa Clara Valley (Cupertino),California,United States
+ Possess in-depth knowledge of memory system
+ Experience in micro-architecture definition and RTL coding, as well as PPA (performance/power/area) analysis.
+ Knowledge of high performance, coherent memory system or interconnect architectures, and DRAM controller.
+ Strong cache design background, including good understanding of different memory organizations and trade-offs.
+ Hands-on experience with multi-processor cache coherence protocols.
You will participate in Cache micro architecture development from specifications found from architecture guideline and model analysis Explore architecture trade-offs in system performance, area, and power consumption along with the performance analysis team Develop/debug RTL design of different sections of the cache controller Work with physical design team to close timing of the same
**Education & Experience**
Bachelor's or Master's in EE/CS/CE
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