Analog Layout Designer
Santa Clara Valley (Cupertino),California,United States
+ Typically requires 8+ years experience in analog/mixed-signal layout design of SubMicron CMOS circuits. Experience in PMU and chip level layout is highly preferred.
+ Experience building tight matching, low capacitance, low power analog blocks, resistors, capacitors, high voltage devices, pad IOs, ESD structures, etc.
+ Proficient experience with custom and standard cell based floor planning and hierarchical layout assembly.
+ Deep understanding of IR drop, RC delay, electro-migration, self-heating and cross capacitance.
+ Looking for strong experience with analog and DFM practices.
+ High-level proficiency in interpretation of Calibre, DRC, ERC, LVS, etc. reports.
+ Knowledge of MENTOR GRAPHICS or CADENCE layout tools.
+ Scripting experience in PERL or SKILL CODE is considered a plus, but not required.
+ Excellent communication skills and able to work with multi-functional teams.
You will be responsible to deliver PDV clean layout, this includes the following: â€¢Working with circuit design team to plan/schedule work and negotiate any necessary layout trade-offs as needed to build complex analog layout in deep SubMicron CMOS technologies. â€¢Recognize failure prone circuit and layout structures. â€¢Running complete set of design verification tools available on Mega-cell level (also on chip level). â€¢Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout. â€¢Exceeding engineering specifications and expectations by working closely with the circuit design teams. â€¢Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area and power requirements.
**Education & Experience**
â€¢BSEE, MSEE, PhD, or equivalent
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