Analog Mixed-Signal IP Designer
Santa Clara Valley (Cupertino),California,United States
+ - Preferred minimum 6 years of experience in IP design integration and implementation with multiple clock domains and multiple power domains.
+ - Deep knowledge and experience in various tools such as RTL simulation, lint, logic equivalence, version control, synthesis, static timing analysis, CDC, RDC in order to generate gate level netlist and perform various checks.
+ - Working experience with the physical design teams
+ - Deep knowledge of VLSI design methodology ranging from RTL to sign-off and familiarity with programming language such as Perl, Tcl, shell scripts
+ - The ideal candidate will be familiar with version control, CVS, Perforce, ClearCase.
+ - Excellent interpersonal skills and interaction experience with sub block owners, physical design teams and different engineering groups
As a senior IP Design/Implementation engineer you will have responsibilities spanning all aspects of IP. You will be responsible for generating gate level netlist and various collaterals for physical design team, lint, logic equivalence check, static low power verification, Functional ECO, CDC, RDC and managing collaterals between front-end design team and physical design team.
**Education & Experience**
MSEE (preferred) or BSEE, or equivalent is required
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