CAD Engineer - PDV (Early Career)
Santa Clara Valley (Cupertino),California,United States
+ Typically requires 1-5 years of industry experience in Silicon chip design flows.
+ Knowledge in Calibre/ICV runset coding for DRC, LVS, ERC, or MFILL.
+ Scripting skills in programming languages such as Perl, Python, Tcl, Shell, Makefile and C.
+ Design debug or tapeout support experience.
+ Understanding in Silicon technology and experience with flow automation.
+ Knowledge of parasitic extraction, SKILL coding, or PnR tools is a plus.
Develop, maintain and improve various aspects of physical verification flow and methodology Automate and validate flows, improving custom checks and data generation Work with the design and PD teams to facilitate the chip design process Code custom PDV rule decks such as Electrical rule checks (ERC) and Programmable ERCs Collaborate with tool vendor and foundries for PDK performance enhancements
**Education & Experience**
BS/MS in EE/CE or equivalent
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