DRAM Design Validation Engineer


Cupertino, CA 95015

Posted 1 month ago

Job Description

DRAM Design Validation Engineer

Santa Clara Valley (Cupertino),California,United States


+ Do you have 3+ years in DRAM development?

+ Are you an expert in DRAM cell architectures?

+ Expert of DRAM memory organization and periphery design for low DRAM power

+ Solid experience in DRAM simulation

+ Experience in memory interface verification with understanding DDR-PHY and Memory Controller

+ Experience in LPDDR IO (DDR/DDR2/DDR3/DDR4) characterization and qualification

+ Knowledge of memory test patterns

+ Knowledge of DRAM reliability

+ Knowledge with state of the art packaging technology (POP, TSV, etc.) and their relationship to DRAM signal/power integrity

+ Previous experience in Failure Analysis of DRAM devices

+ Excellent hardware and software debug skill

+ Experience working with the major DRAM memory vendors

+ Strong background in computer architecture

+ Programming experience in C/C++ Excellent interpersonal skills and teamwork abilities


- Working with design, verification and integration engineers to ensure memory controller requirements are well-defined and cover the scope of DRAM based corner cases - Collaborating with Architecture and DRAM vendors for Apple’s main memory solution - Ensuring DRAM simulation meets Apple's requirements - Ensuring the internal and external DRAM silicon and package level testing meets Apple's requirements - Drive the validation and qualification of DRAM with the memory vendors - Debugging RMA material with apparent DRAM related defects - Collaborating with the DRAM vendors to improve test coverage - Drive roadmaps and specs of memory vendors for next technology node devices

**Education & Experience**

PhD, MS or BS Degree in technical discipline

**Additional Requirements**

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