Digital Design Engineer


Cupertino, CA 95015

Posted 1 month ago

Job Description

Digital Design Engineer

Santa Clara Valley (Cupertino),California,United States


+ Typically requires 8+ years or more experience in digital design including RTL design experience

+ Ability to analyze a design and partition between HW implementation and SW control

+ Knowledge of standard methodologies with respect to implementation of digital logic

+ Understanding of digital design flow including RTL simulation, logic synthesis, timing constraints, timing closure, STA, back annotation of parasitics, gate level simulation, equivalence checking

+ Understanding of Design Verification and the ability to write self-checking test suites Ability to analyze a design and partition between HW implementation and SW control

+ Experience in hands-on lab evaluation

+ Understanding of ASIC test methodology such as scan insertion, memory BIST trim / cal test sort & class test and test pattern generation

+ Experience in hands-on lab evaluation


•Work with system and SoC teams to understand the top level requirements of the digital functions and develop detailed specifications •Implement the function in Verilog RTL to specification •Partition the function between HW and FW for most efficient implementation •Develop RTL and FW to implement the function •Perform unit level testing on the RTL function Other responsibilities could include: •RTL synthesis •Equivalence checking •Static Timing Analysis •Integration of hard and soft IP •Support the DV team by writing self-checking tests as required •Develop FW to support DV and ATE environments

**Education & Experience**

•MSEE required

**Additional Requirements**

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