Formal Verification Engineer
Santa Clara Valley (Cupertino),California,United States
+ Advanced knowledge of SoC/CPU/GPU designs, VLSI, and digital logic design and verification techniques
+ Developed formal property proofs on industrial strength designs and architectures
+ Deep understanding of pipeline architectures, memory/DMA controllers, out-of-order and speculative instruction execution hardware, bus interconnects, and cache coherence mechanisms
+ Confirmed understanding of formal verification technologies/abstraction techniques
+ Knowledge and experience in interpreting hardware specifications and using
+ Temporal logic assertion-based languages such as SVA or PSL
+ Experience in using EDA formal tools and tool development experience is a plus
+ Proficiency in any scripting language with excellent debugging skills
+ Extraordinary teammate with excellent interpersonal skills
+ Passionate about developing world-class/innovative formal verification solutions
As a formal verification architect leading the complete formal verification for single or multiple design blocks and IPâ€™s (CPU, Media IP, Security IP, Peripheral IP, Interconnects, Power management subsystems, etc.), you will be responsible for: Working with Apple's world-class SOC and IP design engineers to develop a formal micro-architecture specification Developing comprehensive formal verification test plan Proving properties of the design, finding design bugs, and working closely with design teams to help improve the micro-architecture Crafting novel and creative solutions for verifying complex design micro- architectures Developing and implementing re-usable and optimized formal models and verification code base Architecting correct-by-construction design methodologies for improved formal verification efficiency and productivity
**Education & Experience**
BS / MS / Ph.D in EE or CS is required.
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