Graphics Cache Hierarchy Design Verification Engineer
Santa Clara Valley (Cupertino),California,United States
+ At least 3-5 years of meaningful experience including: Experience developing unit or cluster level test environments
+ Experience defining and executing unit level test plans. Expertise with verification languages such as SystemVerilog
+ Experience with common verification methodologies such as UVM.
+ Expertise with HDL simulators and waveform viewers.
+ Experience defining coverage space, writing coverage and coverage closure
+ Experience working under strict schedule deadlines with the ability to manage multiple priorities
+ Strong fundamental software and programming skills
+ Experience with cache verification and memory subsystem testing highly desired. Graphics architecture a plus.
+ Experience with Perl, Ruby, Shell scripting, Makefiles a plus.
- Develop verification plans in coordination with design leads and architects. - Build and maintain portable verification test bench components and environments. - Generate directed and constrained random tests. - Run simulations and debug design and environment issues. - Create functional coverage points, analyze coverage, and improve test environment to target coverage holes. - Create automated verification flows for block verification. - Apply knowledge of hardware description languages (VHDL/Verilog) to verify complex designs. - Work with other block, memory subsystem and core level engineers to ensure seamless verification flow.
**Education & Experience**
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