Capgemini is an Equal Opportunity Employer encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law.
This is a general description of the Duties, Responsibilities and Qualifications required for this position. Physical, mental, sensory or environmental demands may be referenced in an attempt to communicate the manner in which this position traditionally is performed. Whenever necessary to provide individuals with disabilities an equal employment opportunity, Capgemini will consider reasonable accommodations that might involve varying job requirements and/or changing the way this job is performed, provided that such accommodations do not pose an undue hardship.
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Capgemini is a global leader in consulting, digital transformation, technology and engineering services. The Group is at the forefront of innovation to address the entire breadth of clients’ opportunities in the evolving world of cloud, digital and platforms. Building on its strong 50-year heritage and deep industry-specific expertise, Capgemini enables organizations to realize their business ambitions through an array of services from strategy to operations. Capgemini is driven by the conviction that the business value of technology comes from and through people. Today, it is a multicultural company of 270,000 team members in almost 50 countries. With Altran, the Group reported 2019 combined revenues of €17billion.
Visit us at www.capgemini.com . People matter, results count.
Design Verification Engineer
In this role you will:
· Implement a state-of-the-art verification environment to facilitate testing of the RTL against reference Matlab/C models
· Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program.
· Work with the design and Communication systems team and participate in System level verification using test benches constructed using UVM, System C and DPI-C.
· Develop a highly automated environment to run regressions that can be used to make builds and maintain the sanity of the database.
. Bachelor's degree in Electrical / Communications Engineering or Computer Science
· 5 to 7 years of experience in verification preferably in communication systems
· Proven track record where products have gone to volume production, preferably 1st pass Silicon.
· Strong written and verbal skills
· Strong problem solving and debugging skills
· Strong proficiency in SystemVerilog, UVM, C, System C and good scripting skills.
· Master's or Ph.D degree in Electrical / Communications Engineering.
· Experience with Verification techniques using Matlab/C/System reference models
· Able to adopt the use of new techniques and methodologies
· Experience in developing coverage-driven verification test plans.
· Familiarity with constrained random and assertion based verification.
Export Control Requirement:
Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.
Candidates should be flexible / willing to work across this delivery landscape which includes and not limited to Agile Applications Development, Support and Deployment.
**Job:** _Project Manager_
**Organization:** _ERD PPL US_
**Title:** _Manager - Design Verification Engineer_
**Location:** _CA-San Diego_
**Requisition ID:** _064489_