Mixed Signal Behavioral Modeling Engineer
Santa Clara Valley (Cupertino),California,United States
+ - Deep knowledge of Verilog/SystemVerilog with ability to write synthesize-able and behavioral code
+ - Deep knowledge of digital logic gates, clocking and state elements
+ - Deep knowledge of HDL simulation
+ - Deep ability to read device level schematics
+ - Deep familiarity with software methods, algorithms and optimization
+ - Deep understanding in writing scripts in PERL/Python
+ - Deep understanding of passive circuit elements, nodal analysis and simple blocks like op-amps
+ - Working knowledge with SPICE simulation and logic equivalence tools is very helpful
+ - Working knowledge of MATLAB desirable
+ - Deep knowledge of systems such as PLLs/DLLs and SERDES blocks is a strong plus
+ - Some working knowledge of numerical probability and statistic is very helpful
In this job you will be responsible for writing behavioral models for custom mixed-signal circuits in SystemVerilog HDL and occasionally C/C++. You will have to write scripts and simple tools for automating repetitive tasks. You will collaborate with circuit design teams to understand fine details of custom circuits, and with DV teams to craft hooks into the behavioral models for effective verification. You will have to run various simulations and equivalence checks to ensure that the model matches closely with the custom circuits.
**Education & Experience**
Preferred MS/PhD in Electrical Engineering with minimum of 5 years of relevant industry experience
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