PHY RTL Design Engineer

Apple

Cupertino, CA 95015

Posted 1 month ago

Job Description

PHY RTL Design Engineer


Santa Clara Valley (Cupertino),California,United States


Hardware


+ 3+ years of verification experience of wireless/wired communication block/subsystem.


+ Excellent knowledge and experience of ASIC verification flow including test bench development, constrained random testing, and code/functional coverage.


+ Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.


+ Experience of using Matlab/C reference model and bit-accurate verification a plus.


+ Knowledge of wireless protocols such as Bluetooth, WLAN, or Zigbee a plus.


+ Proficient in shell and Perl scripting, Python skills a plus.


+ Experience of Palladium/FPGA validation a plus.


+ Should be a team player with excellent communication skills, self-motivated and well organized.


**Description**


Develop signal processing intensive design for wireless communication SoCs, including: - Writing specifications and other documents based on MATLAB/C system model - Microarchitecture definition - IP integration, RTL logic design, and DV support - Running tools to ensure lint-free and CDC clean design - Synthesis and timing constraints - Work with algorithm and software team to ensure performance and power efficiency


**Education & Experience**


MSEE, Ph.D. preferred


**Additional Requirements**


+ Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.


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