PHY RTL Design Engineer
Santa Clara Valley (Cupertino),California,United States
+ 3+ years of verification experience of wireless/wired communication block/subsystem.
+ Excellent knowledge and experience of ASIC verification flow including test bench development, constrained random testing, and code/functional coverage.
+ Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
+ Experience of using Matlab/C reference model and bit-accurate verification a plus.
+ Knowledge of wireless protocols such as Bluetooth, WLAN, or Zigbee a plus.
+ Proficient in shell and Perl scripting, Python skills a plus.
+ Experience of Palladium/FPGA validation a plus.
+ Should be a team player with excellent communication skills, self-motivated and well organized.
Develop signal processing intensive design for wireless communication SoCs, including: - Writing specifications and other documents based on MATLAB/C system model - Microarchitecture definition - IP integration, RTL logic design, and DV support - Running tools to ensure lint-free and CDC clean design - Synthesis and timing constraints - Work with algorithm and software team to ensure performance and power efficiency
**Education & Experience**
MSEE, Ph.D. preferred
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