Physical Design Verification Engineer
Santa Clara Valley (Cupertino),California,United States
+ - Preferred 5+ years of experience in IP design integration and physical design verification
+ - Deep knowledge and experience in various tools such as RTL simulation, lint, logic equivalence, version control, synthesis, static timing analysis, CDC, RDC in order to generate gate level netlist and perform various checks.
+ - Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc., working experience CVS, Perforce, ClearCase.
+ - Strong knowledge of physical verification flows and methodology
+ - Scripting skills to debug flow related issues and make improvements as appropriate
+ - Real chip tapeout experience with a track record of successful signoff
+ - Layout design background and experience a plus
+ - Excellent interpersonal skills and interaction experience with sub block owners, physical design teams and different engineering groups
As a physical design verification engineer, you will have responsibilities spanning all aspects of IP. Your tasks includes but not limited to performing various types of physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography) at the chip and block level. You will be working closely with the CAD/Technology teams for flow bring up and validation, collaborating with the Implementation team during the entire chip design cycle to drive signoff closure for tapeout. You will get to own schedules and support cross-functional engineering effort. You will also get to collaborate with the package and floorplan teams.
**Education & Experience**
MSEE (preferred) or BSEE, or equivalent is required
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