SoC Memory Performance Architect
Santa Clara Valley (Cupertino),California,United States
+ You will have experience/skills in several of the following areas:
+ Strong knowledge of memory controller techniques for different memory technologies such as DDRx and LPDDRx.
+ Prior work on analyzing the memory access patterns and bandwidth/latency requirements of Camera, Video, Graphics, or Machine Learning hardware accelerators.
+ Demonstrated ability of SoC architecture and microarchitecture performance modeling and studies.
+ Excellent C/C++/scripting coding, debug, and testing skills.
+ Expertise in cooperative code development using a revision control system such as GIT.
+ Experience with Cellular/5G modem architecture is a plus.
+ Strong communication and documentation skills.
You will have responsibilities for developing the SoC hardware solutions that drive the architecture of Apple’s future System-on-Chips. Your work will be highly visible and critical to delivering the best performance and power efficiency in Apple’s future products. You will be expected to collaborate with all the hardware and software teams that are part of Apple’s SoC development: - C++ performance modeling of proposed architectural solutions and features. - Writing architectural specification documents in collaboration with engineers across different disciplines. - Gathering, analyzing, and validating measured and simulated results to compare architectural design alternatives. - Work with the multi-functional teams to develop architectural solutions. - Improve Apple’s modeling platform by developing APIs, tools, and optimal standard examples that can be used throughout the company. - Carefully analyze and present results to enable data specific architecture/design. - Measure and analyze existing SOC and workloads. - Some international travel is required for this position.
**Education & Experience**
MS or PhD in CS, EE, or related field.
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