SoC Packaging Engineer
Santa Clara Valley (Cupertino),California,United States
+ 5+ years experience in Semiconductor Packaging Process, Design and Material development.
+ Expert in packaging assembly processes including SMT, die prep, die attach, flip chip, underfilling, wire bonding, molding, singulation and back-end processes.
+ Expert in materials characterization and analysis, DOE, reliability standards and FA techniques.
+ Excellent communication skills that can enable the candidate to work well with internal cross functional teams and overseas suppliers.
+ Ability to work independently and take on projects with minimum supervision.
+ Excellent engineering problem solving with strong physics and fundamentals.
+ Familiar with package design software, APD, etc.
+ Working knowledge in memory device architecture, design, test, etc.
+ Strong program management skills
â€¢Responsible leading packaging assembly technology development. â€¢Work with cross functional team and lead SoC Package integration and architecture efforts. â€¢Work with foundry and OSAT to bring packaging solution from concept to HVM. â€¢Drive industry with advanced Package solutions, new material development, and specs. â€¢5 % International travel.
**Education & Experience**
â€¢Ph.D. or M.S. in Chemical Engineering, Materials Science, Mechanical Engineering, or Physics.
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