Sr. CAD Engineer– Design Verification Methodology

Apple

Portland, OR 97240

Posted 1 month ago

Job Description

Sr. CAD Engineer– Design Verification Methodology


Portland,Oregon,United States


Hardware


+ We typically require at least 10+ years of experience with MSEE/CE/CS preferred


+ Working knowledge of Verilog and/or SystemVerilog


+ Knowledge of SQL style databases and query language preferred.


+ Strong experience with Synopsys VCS, Incisive/Xcelium, or Modelsim


+ Strong programming abilities in Python and/or PERL are required; We consider Java and TCL a plus


+ Good communication skills are required and prior user support experience is a plus


+ Experience with front end web development and UI is a plus


+ Experience with UVM, VMM or OVM a plus


+ Familiarity with Verdi, Indago and/or Simvision is considered a plus


+ Knowledge of C and C++ preferred


**Description**


On our team, you will: - Develop, deploy, and support robust, configurable, and scalable tools to enable hardware verification across multiple projects - Identify, capture, and analyze metrics for improved automation reliability and hardware verification performance - Help to debug vendor tool issues - Interact with the DV team to help tackle their problems - Implement new functionality to solve emerging problems or to optimize already existing methods


**Education & Experience**


MSEE/CE/CS


**Additional Requirements**


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