Wireless FPGA Design Engineer
Santa Clara Valley (Cupertino),California,United States
+ 6+ years of hands-on experience
+ Good knowledge in modern design techniques and SOC, ASIC implementation
+ Experienced with large FPGA development on Xilinx or Altera devices
+ Very familiar with Xilinxâ€™s build flow including design entry in Verilog, synthesis, place and route, timing constraints and timing closure
+ Experience with verification methodologies, RTL and gate level simulation and debug
+ Hands on experience with lab debug equipment, such as oscilloscopes and logic analyzer
+ Proven background in computer architecture including one or more of the followings:
+ 1. Bus fabric, especially APB/AHB/AXI
+ 2. Tiered memory systems
+ 3. System debug architecture
+ 4. Power management with multiple power domains
+ 5. Tiered memory systems
+ 6. System debug architecture
+ 7. Power management with multiple power domains
+ Track record of bringing logic designs into mass production
+ Ability to work well in a team and be productive under tight schedules
+ Excellent interpersonal skills and self-motivation/organization
+ Experience with emulation platform desired
+ Ability to drive strong production test/QA methodologies a plus
In this role, you will develop signal processing intensive design for wireless communication SoCs, including: System- and hardware-level definition ASIC prototyping from requirement to implementation and debug FPGA Synthesis and timing constraints, timing closure Experience with industry-standard protocol(USB, I2C, SPI, etc) Synchronizing between SW, verification and design groups
**Education & Experience**
BS required, MSEE/PhD preferred.
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