Wireless Low Power RTL Design Engineer
Santa Clara Valley (Cupertino),California,United States
+ We'd like you to have:
+ 5 or more years of experiences in SoC integration and Low Power ASIC design
+ Proficiency in ASIC logic design
+ Extensive experience with SoC power management design
+ SoC level power related design verification experience
+ Deep understanding of ASIC low power design techniques, e.g. Power analysis, UPF, VCLP
+ SoC level clock mesh / reset design experience desirable
+ Proficiency in scripting languages (Shell and Perl highly desirable, Python skills are a plus)
+ SoC top-level integration experience is a plus
+ System architecture knowledge is a bonus
+ Strong abilities to solve problems
In this role, you are going to develop signal processing intensive design for wireless communication SoCs, including: - Complex SoC low power design, analysis and implementation - Writing specifications and other documents - IP integration, RTL logic design, and DV support - Running tools to ensure lint-free and CDC clean design - Synthesis and timing constraints
**Education & Experience**
BS required, MSEE/PhD preferred
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