Wireless RTL Design Engineer
Santa Clara Valley (Cupertino),California,United States
+ We'd like you to have:
+ 7+ years of hands-on experience
+ Strong fixed-point knowledge and extensive experience with bit-true verifications
+ Understanding of DSP communication algorithms and trade-offs between performance and complexity
+ Good knowledge in modern design techniques and energy-efficient/low power logic design
+ Solid background in computer architecture including one or more of the following: Bus fabric, especially APB/AHB/AXI, Tiered memory systems, System debug architecture.
+ Power management with multiple power domains, Integer and floating-point numeric units
+ High-speed data path and control units
+ Track record of bringing logic designs into mass production.
+ Ability to work well in a team and be productive under aggressive schedules
+ Excellent communication skills and self-motivation/organization
+ Experience with FPGA and/or emulation platform desired
+ Ability to drive strong production test/QA methodologies a plus
In this role, you will develop signal processing intensive design for wireless communication SoCs, including: â€¢ Writing specifications and other documents based on MATLAB/C system model â€¢ Microarchitecture definition â€¢ IP integration, RTL logic design, and verification support â€¢ Running tools to ensure lint-free and CDC clean design â€¢ Synthesis and timing constraints â€¢ Collaboration with algorithm and software team to ensure performance and power efficiency
**Education & Experience**
BS required, MSEE/PhD preferred
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